1. Technical Field
The present invention relates generally to static memory circuits, and more particularly to a method for evaluating the dynamic stability of static memory cell designs.
2. Description of the Related Art
Memory speed and other performance factors are critical limitations in today's processing systems and are predicted to become even more of a critical limitation as technologies move forward. In particular, static random access memories (SRAMS) and memory cells are used in processor caches, registers and in some designs external to the system processors for fast access to data and program instructions.
With processor cycle frequencies reaching well above 4 Ghz, development of SRAM cells that can store and provide access to stored values within that period has become necessary. However, process scales necessary to achieve such access times are also increasingly subject to variability in circuit parameters such as device threshold voltages and channel dimensions. The variability is present both with respect to parameters of each die and across the production process where die-to-die variation must also be controlled, but tolerated within the robustness of the circuit design. Further, negative bias temperature instability (NBTI) provides another variable that changes over circuit lifetime and dictates a minimum voltage at which the cell state can be toggled during the entire lifetime of the circuit.
Present techniques for evaluating the AC performance of memory cells typically analyze the cell using a static “butterfly” curve to evaluate static margins of the cell signals. The butterfly curve describes the switching action of a cross-coupled inverter pair that provide the static memory cell function. The static butterfly curve analysis is not adequate for analyzing memory circuits scaled for operation at the above-mentioned frequencies, as dynamic effects in the devices are increasingly important as operating frequencies are increased and power supply voltages are decreased.
It is therefore desirable to provide a method and circuit for evaluating static memory cell performance as process size and power supply voltages are decreased.